Dynamic Random Access Memory (DRAM) cells are well known. A DRAM cell is essentially a capacitor for storing charge and a pass transistor (also called a pass gate) for transferring charge to and from the capacitor. Because cell size determines chip density, size and cost, reducing cell area is the DRAM designer's primary goal. Reducing cell area is done, normally, by reducing feature size to shrink the cell.
Besides shrinking the cell, the most effective way to reduce cell area is to reduce the largest feature in the cell, typically, the area of the storage capacitor. Unfortunately, shrinking the capacitor area reduces capacitance and, consequently, reduces stored charge. Reduced charge means what is stored in the DRAM is more susceptible to noise, soft errors, leakage and other typical DRAM problems. Consequently, a DRAM cell designer's goal is to maintain storage capacitance without sacrificing cell area.
One way to accomplish this goal for high density DRAMs is to use trench capacitors in the cell. Trench Capacitors are formed by placing the capacitor on its side, in a trench, and are vertical with respect to the chip's surface. Thus, the space required for the storage capacitor is dramatically reduced without sacrificing capacitance, and more importantly, stored charge.
FIG. 1 is an example of prior art trench capacitor DRAM cells and FIG. 2 is a cross sectional view of the DRAM cells of FIG. 1. Each cell 100 is isolated from other cells 100 by a deep trench 102. A polysilicon layer 104 in the trench 102 encircles each cell 100 and is the storage plate of the cell's storage capacitor. A layer of oxide 106 separates each storage plate 104 from a layer of polysilicon 108 (poly) separating cells 100 and forming the storage capacitors' reference plate. A buried polysilicon contact 110 is formed after the pass gate, a Field Effect Transistor (FET), is defined. The contact 110 provides the pass gate's source and straps the FET's source to the poly storage plate 104. A polysilicon word line 112 forms the FET's gate, with its drain 114 connected to bit line contact 116. Thus, as can be seen from the above example, using a trench capacitor eliminates much of the cell area, i.e. cell area formerly reserved for the storage capacitor. However, forming the strap between the pass gate and the capacitor is a delicate operation.
One approach to making this strap, i.e. between the cell's storage plate and the cell's pass gate is disclosed in U.S. Pat. No. 5,049,518 to Fuse entitled "Method of Making a Trench DRAM Cell", incorporated herein by reference. Fuse discloses a DRAM cell with a trench storage capacitor wherein the storage capacitor is connected to the pass gate by using a fine trench polysilicon burying method or by using a selective epitaxial method. After the gate is formed in the Fuse method, a fine trench is formed along the deep trench edge, between the pass gate's source/drain and the trench storage capacitor's polysilicon storage plate. The fine trench is filled with polysilicon to form the strap between the storage plate and the existing pass gate source/drain. Consistently, strapping the trench capacitor to the pass gate according to the Fuse method is difficult, because the fine trench (defined by the overlay of a photoresist opening with the edge of the trench) must be kept thin enough, so that the DRAM cell size does not increase, but, still, wide enough and deep enough that polysilicon can be deposited in the opening to contact the polysilicon capacitor electrode. By eliminating storage surface capacitor area as a major factor in cell area, cell feature size, already a primary factor in cell area, again became the focus in DRAM cell design.
However, as features shrink, it becomes increasingly difficult to strap the storage capacitor to the transfer gate. Further, reliability of this connection drops, reducing chip yield. Another reason it is difficult to form the strap is because, it is formed after the gate. Once the gate is formed, the wafer's surface is not smooth. Instead, the surface is filled with relatively large peaks and valleys resulting from prior transistor definition steps. This uneven topography makes it more difficult to focus on alignment targets and much more difficult to align upper layers with layers defined much earlier, when the wafer was still smooth and buried under this uneven topography.
Finally, etching required to open the fine trench attacks oxide protecting the pass gate, introducing gate defects. For example, plasma etching can result in damage to gate oxide from high energy ion bombardment.